Compared with silicon (Si), silicon carbide (SiC) has a number of superior properties, such as 1. a wider bandgap, 2. a higher dielectric breakdown strength and 3. a higher electron saturation drift velocity. As such, using silicon carbide as a substrate material makes it possible to manufacture low-resistance power semiconductor devices having much higher blocking voltages than silicon has. Also, as in the case of silicon, thermal oxidation can be used to form an insulation layer on silicon carbide. For this reason, considerable research and development is being conducted into producing vertical MOSFETs having a low ON-resistance and high blocking voltages, using silicon carbide as the substrate material.
FIG. 12 is a schematic cross-sectional view for explaining a unit cell of a typical planar vertical MOSFET. In FIG. 12, a low concentration n-type drift layer 2 is deposited on a high concentration n+ substrate 1. In the low concentration n-type drift layer 2, a p-type well layer 3 is selectively formed from the surface. There is a low concentration n-type base region 4 between the well layers 3.
A high concentration n+ source region 5 is also selectively formed in the p-type well layer 3 from the surface. A gate insulation film 6 is formed on the surface of the low concentration n-type base region 4 and on the surface of the portion of the p-type well layer flanked by the high concentration n+ source region 5, and a gate electrode 7 is provided on the gate insulation film 6. An interlayer insulation film 8 is formed on the gate electrode 7, and a source electrode 9 is formed on the interlayer insulation film 8 and has a low-resistance connection with a portion of the surface of the high concentration n+ source region 5 and with a portion of the surface of the p-type well layer 3.
A drain electrode 10 is formed on the backside of the high concentration n+ substrate 1. When a gate voltage that is a threshold voltage or higher is applied to the gate electrode 7 of the planar vertical MOSFET having this structure, electrons are induced to the surface of the p-type well layer 3, forming an n-type inversion layer in the surface layer of a channel region 11. This produces a state of electrical continuity between the high concentration n+ source region 5 and the low concentration n-type drift layer 2, enabling an electric current to flow from the drain electrode 10 to the source electrode 9.
When the gate voltage is lower than the threshold voltage, the high concentration n+ source region 5 and the low concentration n-type drift layer 2 enter an insulated state. When a voltage is applied to the drain electrode 10 in this state, the low concentration n-type base region 4 is pinched off by a depletion layer that extends from the junction between the p-type well layer 3 and the low concentration n-type base region 4. If the voltage to the drain electrode 10 is increased, the depletion layer extends to within the low concentration n-type drift layer 2. The maximum applied voltage is limited by the thickness of the low concentration n-type drift layer 2, determining the blocking voltage of the device.
When the substrate material is silicon, the planar type vertical MOSFET is manufactured by the double diffusion method. FIGS. 13(a) to 13(f) and FIGS. 14(a) and 14(b) are views for explaining the method of manufacturing a planar type vertical MOSFET by the double diffusion method. First, a low concentration n-type drift layer 2 is deposited on the surface of a high concentration n+ substrate 1. Then, oxidation is used to form a gate insulation film 6 on the surface of the low concentration n-type drift layer 2.
Polycrystal silicon 7a is deposited on the gate insulation film 6, producing the state shown in FIG. 13(a). Photolithography is then used to pattern-process the polycrystal silicon 7a to form gate electrode 7, as shown in FIG. 13(b). Next, as shown in FIG. 13(c), selective p-type impurity ion implantation 3a is carried out, using the gate electrode 7 as a mask.
Thermal diffusion is then used to form a p-type well layer 3, as shown in FIG. 13(d). A p-type impurity such as boron or the like that has a high diffusion coefficient will penetrate under the mask. Then, as shown in FIG. 13(e), ion implantation 5a of an n-type impurity such as phosphorus is carried out, using the same mask. Thermal diffusion is then used to form the high concentration n+ source region 5, shown in FIG. 13(f).
An n-type impurity such as phosphorus has a smaller diffusion coefficient than a p-type impurity such as boron, so a channel region 11 is formed by the difference in diffusion length in the horizontal direction, as shown in FIG. 14(a). Next, the CVD method is used to form interlayer insulation film 8 on the surface, and a window is formed in the interlayer insulation film 8. As shown in FIG. 14(b), source electrode 9 is then provided on the surfaces of the high concentration n+ source region 5 and the p-type well layer 3 with a low-resistance contact connection.
In this planar type vertical MOSFET using silicon, manufactured using double diffusion, to ensure that conduction electrons in the channel that are induced to the surface layer of the channel region 11 are not scattered by crystal defects and the like caused by ion implantation and the like, they are given a high channel mobility of several hundred cm2/Vs, which provides low ion resistance.
In contrast, when a silicon carbide substrate (high concentration n+ substrate) 1 is used, the planar type vertical MOSFET having the structure shown in FIG. 12 cannot be manufactured using the double diffusion method illustrated by FIGS. 13 and 14. This is because inside the silicon carbide substrate (low concentration n-type drift layer) 2, the diffusion coefficient of the impurity elements is very small, so the channel region 11 cannot be formed by the difference in the horizontal diffusion lengths of the p-type and n-type impurities.
Generally, a silicon carbide planar type vertical MOSFET is manufactured by the double ion implantation method, described below. FIGS. 15(a) to 15(f) and FIGS. 16(a) and 16(b) illustrate the method of manufacturing a typical planar type vertical MOSFET using the conventional double ion implantation method. With reference to FIG. 15(a), first, a low concentration n-type drift layer 2 is formed on a silicon carbide n+ substrate (high concentration n+ substrate) 1. As shown in FIG. 15(b), a mask 12 is provided on the surface of the low concentration n-type drift layer 2.
By means of the mask 12, the low concentration n-type drift layer 2 is subjected to selective implantation of p-type impurity ions 3a. If the implantation acceleration voltage is raised at this time, the p-type impurity ion implantation 3a penetrates deep into the low concentration n-type drift layer 2. Next, as shown in FIG. 15(c), the low concentration n-type drift layer 2 is provided with different-size masks 13, which are used for selective implanting of n-type impurity ions 5a. 
The acceleration voltage at this time is set to one at which the range distance of the n-type impurity ions 5a is smaller than that of the p-type impurity ions 3a. As shown in FIG. 15(d), when the masks 13 have been removed, heat treatment is used to activate the implanted-ion region and form high concentration n+ source region 5 and p-type well layer 3. As the diffusion of the implanted ions by the heat treatment is very low, the profile of the implanted ions remains substantially the same for each layer.
Following this, thermal oxidation is used to form a gate insulation film 6 on the surface, as shown in FIG. 15(e). Also, polycrystal silicon or metal 7a is deposited on the gate insulation film 6. Photolithography is used to form gate electrode 7 from the polycrystal silicon or metal 7a, as shown in FIG. 15(f). Next, the CVD method is used to form interlayer insulation film 8 on the surface of the gate electrode 7, and a window is formed in the interlayer insulation film 8, as shown in FIG. 16(a). As shown in FIG. 16(b), source electrode 9 is then provided on the surfaces of the high concentration n+ source region 5 and p-type well layer 3 with a low-resistance contact connection.
Since with this method the channel region 11 is formed by ion implantation, it includes many crystal defects arising from the ion implantation. Also, the implanted p-type impurity elements are not adequately electrically activated even by applying heat treatment at high temperatures above 1600° C. Therefore, in order to obtain a sufficient impurity concentration, it is necessary to increase the injection amount, which increases the amount of defects that are produced.
As a result, the conduction electrons in the channel are scattered by these defects and the like, reducing mobility. Thus, a problem with silicon carbide planar type vertical MOSFETs manufactured by the double ion implantation method is that channel mobility is 1 cm2/Vs or lower, which is very low, and the ON-resistance is far higher than the theoretical level.
Ways of reducing the ON-resistance of silicon carbide planar MOSFETs include forming the channel region 11 by deposition rather than ion implantation, as described in the Journal of Applied Physics, vol. 87, 8773 (2000). FIG. 17 is a cross-sectional schematic view for explaining the unit cell structure of such a MOSFET. In the MOSFET of FIG. 17, a low concentration n-type drift layer 2 is deposited on a high concentration n+ substrate 1, a high concentration p+ layer 31 is deposited on the drift layer 2, and a low concentration p-type layer 32 is selectively deposited on the layer 31. Then, implantation of n-type impurity ions is used to selectively form a low concentration n-type base region 4 that extends through the high concentration p+ layer 31 and low concentration p-type layer 32 to the low concentration n-type drift layer 2. A high concentration n+ source region 5 is then selectively formed on the surface of the low concentration p-type layer 32.
The portions of the high concentration p+ layer 31 and the low concentration p-type layer 32 that are not thus implanted with n-type impurity ions form p-type well layer 3. Since in the case of this structure the channel region 11 is formed in a deposition film in which ions have not been implanted, conduction electrons having a high mobility can be obtained. Here, the p-type layer 32 is given a relatively low concentration in order to obtain high channel mobility.
There is a published report (IEEE Electron Device Letters, vol. 22, 272 (2001)) of high channel mobility being obtained in an actual silicon carbide planar type vertical MOSFET fabricated on a 5×1015 cm−3 low concentration p-type deposition film. It is necessary for the p+ layer 31 to have a relatively high concentration, because if it has a low concentration its thickness has to be increased to one in the order of several microns to prevent punch-through at low voltages between the high concentration n+ source region 5 and the low concentration n-type drift layer 2. Doing that means that the acceleration voltage for the implantation of n-type impurity ions for forming the low concentration n-type base region 4 becomes very high, in the MeV range, making it difficult to manufacture an apparatus using an ordinary apparatus. It can be considered that punch-through can be prevented and the structure made able to have high blocking voltages by making the concentration of the p-type layer 31 relatively high and reducing the thickness of the layer. The above cited references that put forward this structure contain no details relating to the manufacturing procedure.
A possible manufacturing method could involve depositing the high concentration p+ layer 31 on the low concentration n-type drift layer 2, and depositing the low concentration p-type layer 32 on the layer 31. This would be followed by using a mask for selective implantation of n-type impurity ions, and heat treatment, to reverse the layer polarity from p-type to n-type and thereby form the low concentration n-type base region 4 bounded by the p-type well layer 3.
Since in this method the channel region 11 is formed by a low concentration p-type deposition film, it should provide a high channel mobility and low ON-resistance. However, increasing the blocking voltage is difficult, for the following reason. The portion 24 where the low concentration n-type base region 4 contacts the low concentration n-type drift layer 2 is a region formed by the implantation of n-type impurity ions in a high concentration p-type deposition film.
In this case, since it is technologically impossible for ion implantation to change a high concentration p-type layer to a p-type layer having a relatively lower concentration, the impurity concentration of the low concentration n-type base region 4 has to be made higher than that of the high concentration p+ layer 31. As a result, the blocking voltage of the pn junction between the low concentration n-type base region 4 formed by the ion implantation and the high concentration p+ layer 31 becomes very low.
When a positive drain voltage is imposed in the voltage suppression state, it is necessary to use a depletion layer to perform full pinch-off by applying a reverse bias to the pn junction between the low concentration n-type base region 4 and the high concentration p+ layer 31. However, when the pn junction has a low blocking voltage, suppression capability is lost at the low voltage level, before pinch-off. When the n-type base region 4 is a high concentration region, there is little spread of the depletion layer so an even higher reverse bias has to be applied to achieve full pinch-off, so the higher voltage makes it even more difficult to suppress the voltage. For the above reasons, this structure is not suitable for obtaining silicon carbide planar type vertical MOSFETs having high blocking voltages.
Since silicon carbide planar type vertical MOSFETs manufactured using double ion implantation includes many crystal defects caused in the channel region by the ion implantation, channel mobility is low and the ON-resistance is not decreased. In contrast, the method in which the channel region is formed of low concentration p-type deposition film increases the channel mobility, and as such can be expected to decrease the ON-resistance. However, since in the structure of silicon carbide planar type vertical MOSFETs proposed up until now, the entire surface of the n-type drift layer is covered by a high concentration p-type deposition film, high concentration n-type impurity ions have to be implanted to form the low concentration n-type base region. This gives rise to the problem that the concentration of the base region is increased, making it impossible to maintain high voltage-suppression capability.
In order to resolve these problems, an object of the present invention is to realize a silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage, by providing in a silicon carbide vertical MOSFET having a gate region a silicon carbide semiconductor apparatus having a low concentration base region for increased blocking voltage (with respect to terminology for characterizing the semiconductor layer impurity concentration or structure and so forth, in terms of function, it is more suitable to describe it as a “gate region,” which has a broader meaning than “channel region,” since the channel region formed by the low concentration p-type deposition film on the surface of the semiconductor layer by gate signals, is very thin, being 0.01 μm thick or thinner, so the semiconductor layer that forms the channel region is much larger than the channel region; so hereinafter “gate region” will be used instead of “channel region”).
Another object of the invention is also to provide a method of manufacturing the silicon carbide semiconductor apparatus with a high blocking voltage having a gate region formed from low concentration p-type deposition film.
A further object of the invention is to provide a silicon carbide semiconductor apparatus having a gate insulation film and gate electrode structure for reducing ON-resistance in a silicon carbide vertical MOSFET with high blocking voltage having a gate region formed from low concentration p-type deposition film.
A further object of the invention is to provide a silicon carbide semiconductor apparatus having a substrate plane orientation for reducing ON-resistance in a silicon carbide vertical MOSFET with high blocking voltage having a gate region formed from low concentration p-type deposition film.